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Power Semiconductor Devices Fundamentals

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Power Semiconductor Devices Fundamentals

Preface excerpt

Today the semiconductor business exceeds $200 billion with about 10% of the revenue derived from power semiconductor devices and smart power integrated circuits. Power semiconductor devices are recognized as a key component for all power electronic systems. It is estimated that at least 50% of the electricity used in the world is controlled by power devices. With the widespread use of electronics in the consumer, industrial, medical, and transportation sectors, power devices have a major impact on the economy because they determine the cost and efficiency of systems. After the initial replacement of vacuum tubes by solid-state devices in the 1950s, semiconductor power devices have taken a dominant role with silicon serving as the base material. These developments have been referred to as the Second Electronic Revolution.

Bipolar power devices, such as bipolar transistors and thyristors, were first developed in the 1950s. Because of the many advantages of semiconductor devices compared with vacuum tubes, there was a constant demand for increasing the power ratings of these devices. Their power rating and switching frequency increased with advancements in the understanding of the operating physics, the availability of larger diameter, high resistivity silicon wafers, and the introduction of more advanced lithography capability. During the next 20 years, the technology for the bipolar devices reached a high degree of maturity. By the 1970s, bipolar power transistors with current handling capability of hundreds of amperes and voltage blocking capability of over 500 V became available. More remarkably, technology was developed capable of manufacturing an individual power thyristorfrom an entire 4-inch diameter silicon wafer with voltage rating over 5,000 V.

TOC

Chapter 1 Introduction 1
1.1 Ideal and Typical Power Switching Waveforms .............................................3
1.2 Ideal and Typical Power Device Characteristics .............................................5
1.3 Unipolar Power Devices ..................................................................................8
1.4 Bipolar Power Devices.................................................................................. 10
1.5 MOS-Bipolar Power Devices........................................................................ 11
1.6 Ideal Drift Region for Unipolar Power Devices ........................................... 14
1.7 Charge-Coupled Structures: Ideal Specific On-Resistance .......................... 16
1.8 Summary ....................................................................................................... 21
Problems........................................................................................................ 21
References ..................................................................................................... 22
Chapter 2 Material Properties and Transport Physics 23
2.1 Fundamental Properties................................................................................. 23
2.1.1 Intrinsic Carrier Concentration......................................................... 25
2.1.2 Bandgap Narrowing.......................................................................... 26
2.1.3 Built-in Potential............................................................................... 30
2.1.4 Zero-Bias Depletion Width .............................................................. 32
2.1.5 Impact Ionization Coefficients ......................................................... 32
2.1.6 Carrier Mobility ................................................................................ 34
2.2 Resistivity...................................................................................................... 51
2.2.1 Intrinsic Resistivity........................................................................... 51
2.2.2 Extrinsic Resistivity.......................................................................... 51
2.2.3 Neutron Transmutation Doping........................................................ 55
2.3 Recombination Lifetime................................................................................ 59
2.3.1 Shockley–Read–Hall Recombination............................................... 60
2.3.2 Low-Level Lifetime.......................................................................... 63
2.3.3 Space-Charge Generation Lifetime .................................................. 65
2.3.4 Recombination Level Optimization.................................................. 66
2.3.5 Lifetime Control ............................................................................... 75
2.3.6 Auger Recombination....................................................................... 80
2.4 Ohmic Contacts ............................................................................................. 82
2.5 Summary ....................................................................................................... 84
Problems........................................................................................................ 84
References ..................................................................................................... 86
Chapter 3 Breakdown Voltage ........................................................................ 91
3.1 Avalanche Breakdown .................................................................................. 92
3.1.1 Power Law Approximations for the Impact Ionization Coefficients 92
3.1.2 Multiplication Coefficient ................................................................ 94
3.2 Abrupt One-Dimensional Diode ................................................................... 95
3.3 Ideal Specific On-Resistance ...................................................................... 100
3.4 Abrupt Punch-Through Diode..................................................................... 101
3.5 Linearly Graded Junction Diode ................................................................. 104
3.6 Edge Terminations ...................................................................................... 107
3.6.1 Planar Junction Termination........................................................... 108
3.6.2 Planar Junction with Floating Field Ring....................................... 120
3.6.3 Planar Junction with Multiple Floating Field Rings ...................... 130
3.6.4 Planar Junction with Field Plate ..................................................... 132
3.6.5 Planar Junction with Field Plates and Field Rings ......................... 137
3.6.6 Bevel Edge Terminations ............................................................... 137
3.6.7 Etch Terminations........................................................................... 148
3.6.8 Junction Termination Extension..................................................... 149
3.7 Open-Base Transistor Breakdown .............................................................. 155
3.7.1 Composite Bevel Termination........................................................ 159
3.7.2 Double-Positive Bevel Termination ............................................... 159
3.8 Surface Passivation ..................................................................................... 162
3.9 Summary ..................................................................................................... 162
Problems...................................................................................................... 163
References ................................................................................................... 164
Chapter 4 Schottky Rectifiers........................................................................ 167
4.1 Power Schottky Rectifier Structure............................................................. 168
4.2 Metal–Semiconductor Contact.................................................................... 169
4.3 Forward Conduction.................................................................................... 171
4.4 Reverse Blocking ........................................................................................ 179
4.4.1 Leakage Current.............................................................................. 180
4.4.2 Schottky Barrier Lowering ............................................................. 181
4.4.3 Prebreakdown Avalanche Multiplication ....................................... 184
4.4.4 Silicon Carbide Rectifiers............................................................... 185
4.5 Device Capacitance ..................................................................................... 187
4.6 Thermal Considerations .............................................................................. 188
4.7 Fundamental Tradeoff Analysis.................................................................. 192
4.8 Device Technology ..................................................................................... 194
4.9 Barrier Height Adjustment.......................................................................... 194
4.10 Edge Terminations ...................................................................................... 197
4.11 Summary ..................................................................................................... 198
Problems...................................................................................................... 199
References ................................................................................................... 200
Chapter 5 P-i-N Rectifiers.............................................................................. 203
5.1 One-Dimensional Structure......................................................................... 204
5.1.1 Recombination Current................................................................... 205
5.1.2 Low-Level Injection Current .......................................................... 206
5.1.3 High-Level Injection Current ......................................................... 208
5.1.4 Injection into the End Regions ....................................................... 217
5.1.5 Carrier–Carrier Scattering Effect.................................................... 219
5.1.7 Forward Conduction Characteristics .............................................. 221
5.2 Silicon Carbide P-i-N Rectifiers ................................................................. 230
5.3 Reverse Blocking ........................................................................................ 232
5.4 Switching Performance ............................................................................... 236
5.4.1 Forward Recovery .......................................................................... 236
5.4.2 Reverse Recovery ........................................................................... 244
5.5
5.6
5.7 P-i-N Rectifier Tradeoff Curves.................................................................. 270
5.8 Summary ..................................................................................................... 274
Problems...................................................................................................... 275
References ................................................................................................... 276
Chapter 6 Power MOSFETs.......................................................................... 279
6.1 Ideal Specific On-Resistance ...................................................................... 280
6.2 Device Cell Structure and Operation .......................................................... 282
6.2.1 The V-MOSFET Structure ............................................................. 283
6.2.2 The VD-MOSFET Structure .......................................................... 284
6.2.3 The U-MOSFET Structure ............................................................. 285
6.3 Basic Device Characteristics....................................................................... 286
6.4 Blocking Voltage......................................................................................... 289
6.4.1 Impact of Edge Termination........................................................... 289
6.4.2 Impact of Graded Doping Profile ................................................... 290
6.4.3 Impact of Parasitic Bipolar Transistor............................................ 291
6.4.4 Impact of Cell Pitch ........................................................................ 293
6.4.5 Impact of Gate Shape...................................................................... 296
6.4.6 Impact of Cell Surface Topology ................................................... 298
6.5 Forward Conduction Characteristics........................................................... 300
6.5.1 MOS Interface Physics ................................................................... 301
6.5.2 MOS Surface Charge Analysis....................................................... 305
6.5.3 Maximum Depletion Width............................................................ 310
6.5.4 Threshold Voltage .......................................................................... 311
6.5.5 Channel Resistance......................................................................... 321
6.6 Power VD-MOSFET On-Resistance .......................................................... 327
6.6.1 Source Contact Resistance.............................................................. 329
6.6.2 Source Region Resistance .............................................................. 330
6.6.3 Channel Resistance......................................................................... 331
6.6.4 Accumulation Resistance................................................................ 332
6.6.5 JFET Resistance.............................................................................. 333
6.6.6 Drift Region Resistance.................................................................. 335
6.6.7 N+ Substrate Resistance .................................................................. 339
6.6.8 Drain Contact Resistance................................................................ 339
6.6.9 Total On-Resistance........................................................................ 340
6.7 Power VD-MOSFET Cell Optimization..................................................... 343
6.7.1 Optimization of Gate Electrode Width........................................... 343
6.7.2 Impact of Breakdown Voltage........................................................ 345
6.7.3 Impact of Design Rules .................................................................. 348
6.7.4 Impact of Cell Topology................................................................. 350
6.8 Power U-MOSFET On-Resistance ............................................................. 358
6.8.1 Source Contact Resistance.............................................................. 359
6.8.2 Source Region Resistance .............................................................. 361
6.8.3 Channel Resistance......................................................................... 361
6.8.4 Accumulation Resistance................................................................ 362
6.8.5 Drift Region Resistance.................................................................. 363
6.8.6 N+ Substrate Resistance .................................................................. 364
6.8.7 Drain Contact Resistance................................................................ 365
6.8.8 Total On-Resistance........................................................................ 365
6.9 Power U-MOSFET Cell Optimization........................................................ 368
6.9.1 Orthogonal P-Base Contact Structure ............................................ 368
6.9.2 Impact of Breakdown Voltage........................................................ 371
6.9.3 Ruggedness Improvement .............................................................. 372
6.10 Square-Law Transfer Characteristics.......................................................... 373
6.11 Superlinear Transfer Characteristics........................................................... 377
6.12 Output Characteristics ................................................................................. 381
6.13 Device Capacitances ................................................................................... 385
6.13.1 Basic MOS Capacitance ................................................................. 386
6.13.2 Power VD-MOSFET Structure Capacitances ................................ 389
6.13.3 Power U-MOSFET Structure Capacitances ................................... 399
6.13.4 Equivalent Circuit........................................................................... 408
6.14 Gate Charge................................................................................................. 409
6.14.1 Charge Extraction ........................................................................... 409
6.14.2 Voltage and Current Dependence................................................... 417
6.14.3 VD-MOSFET vs. U-MOSFET Structure ....................................... 421
6.14.4 Impact of VD-MOSFET and U-MOSFET Cell Pitch .................... 423
6.15 Optimization for High Frequency Operation.............................................. 426
6.15.1 Input Switching Power Loss........................................................... 427
6.15.2 Output Switching Power Loss ........................................................ 432
6.15.3 Gate Propagation Delay.................................................................. 434
6.16 Switching Characteristics............................................................................ 436
6.16.1 Turn-On Transient .......................................................................... 437
6.16.2 Turn-Off Transient.......................................................................... 440
6.16.3 Switching Power Losses................................................................. 443
6.16.4 [dV/dt] Capability ........................................................................... 443
6.17 Safe Operating Area .................................................................................... 447
6.17.1 Bipolar Second Breakdown............................................................ 449
6.17.2 MOS Second Breakdown ............................................................... 451
6.18 Integral Body Diode .................................................................................... 452
6.18.1 Reverse Recovery Enhancement .................................................... 453
6.18.2 Impact of Parasitic Bipolar Transistor............................................ 453
6.19 High-Temperature Characteristics .............................................................. 454
6.19.1 Threshold Voltage .......................................................................... 454
6.19.2 On-Resistance ................................................................................. 455
6.19.3 Saturation Transconductance.......................................................... 456
6.20 Complementary Devices ............................................................................. 457
6.20.2 On-Resistance ................................................................................. 458
6.20.3 Deep-Trench Structure.................................................................... 459
6.21 Silicon Power MOSFET Process Technology............................................ 460
6.21.1 Planar VD-MOSFET Process......................................................... 460
6.21.2 Trench U-MOSFET Process........................................................... 462
6.22 Silicon Carbide Devices.............................................................................. 465
6.22.1 The Baliga-Pair Configuration ....................................................... 465
6.22.2 Planar Power MOSFET Structure .................................................. 476
6.22.3 Shielded Planar Power MOSFET Structures.................................. 481
6.22.4 Shielded Trench-Gate Power MOSFET Structure ......................... 489
6.23 Summary ..................................................................................................... 498
Problems...................................................................................................... 499
References ................................................................................................... 503
Chapter 7 Bipolar Junction Transistors....................................................... 507
7.1 Power Bipolar Junction Transistor Structure.............................................. 508
7.2 Basic Operating Principles.......................................................................... 510
7.3 Static Blocking Characteristics ................................................................... 513
6.20.1 The p-Channel Structure................................................................ 458
7.3.1 Open-Emitter Breakdown Voltage ................................................. 514
7.3.2 Open-Base Breakdown Voltage ..................................................... 514
7.3.3 Shorted Base–Emitter Operation .................................................... 516
7.4 Current Gain................................................................................................ 520
7.4.1 Emitter Injection Efficiency ........................................................... 522
7.4.2 Emitter Injection Efficiency with Recombination
in the Depletion Region .............................................................................. 526
7.4.3 Emitter Injection Efficiency with High-Level Injection
in the Base ................................................................................................... 528
7.4.4 Base Transport Factor..................................................................... 533
7.4.5 Base Widening at High Collector Current Density ........................ 536
7.5 Emitter Current Crowding........................................................................... 550
7.5.1 Low-Level Injection in the Base .................................................... 551
7.5.2 High-Level Injection in the Base.................................................... 555
7.5.3 Emitter Geometry ........................................................................... 559
7.6 Output Characteristics ................................................................................. 560
7.7 On-State Characteristics.............................................................................. 565
7.7.1 Saturation Region ........................................................................... 566
7.7.2 Quasisaturation Region................................................................... 571
7.8 Switching Characteristics............................................................................ 574
7.8.1 Turn-On Transition......................................................................... 575
7.8.2 Turn-Off Transition ........................................................................ 588
7.9 Safe Operating Area .................................................................................... 607
7.9.1 Forward-Biased Second Breakdown .............................................. 608
7.9.2 Reverse-Biased Second Breakdown............................................... 611
7.9.3 Boundary for Safe Operating Area................................................. 615
7.10 Darlington Configuration ............................................................................ 616
7.11 Summary ..................................................................................................... 619
Problems...................................................................................................... 619
References ................................................................................................... 621
Chapter 8 Thyristors ...................................................................................... 625
8.1 Power Thyristor Structure and Operation ................................................... 628
8.2 Blocking Characteristics ............................................................................. 631
8.2.1 Reverse-Blocking Capability.......................................................... 632
8.2.2 Forward-Blocking Capability ......................................................... 636
8.2.3 Cathode Shorting ............................................................................ 641
8.2.4 Cathode Shorting Geometry ........................................................... 644
8.3 On-State Characteristics.............................................................................. 651
8.3.1 On-State Operation ......................................................................... 652
8.3.2 Gate-Triggering Current ................................................................. 654
8.3.3 Holding Current .............................................................................. 657
8.4 Switching Characteristics............................................................................ 662
8.4.1 Turn-On Time................................................................................. 663
8.4.2 Gate Design..................................................................................... 671
8.4.3 Amplifying Gate Design................................................................. 672
8.4.4 [dV/dt] Capability ........................................................................... 675
8.4.5 Turn-Off Process ............................................................................ 683
8.5 Light-Activated Thyristors.......................................................................... 685
8.5.1 [dI/dt] Capability ............................................................................ 686
8.5.2 Gate Region Design........................................................................ 687
8.5.3 Optically Generated Current Density ............................................. 688
8.5.4 Amplifying Gate Design................................................................. 690
8.6 Self-Protected Thyristors ............................................................................ 691
8.6.1 Forward Breakdown Protection...................................................... 691
8.6.2 [dV/dt] Turn-On Protection ............................................................ 694
8.7 The Gate Turn-Off Thyristor Structure....................................................... 698
8.7.1 Basic Structure and Operation........................................................ 698
8.7.2 One-Dimensional Turn-Off Criterion............................................. 701
8.7.3 One-Dimensional Storage Time Analysis ...................................... 703
8.7.4 Two-Dimensional Storage Time Model......................................... 704
8.7.5 One-Dimensional Voltage Rise Time Model................................. 706
8.7.6 One-Dimensional Current Fall Time Model .................................. 709
8.7.7 Switching Energy Loss................................................................... 721
8.7.8 Maximum Turn-Off Current........................................................... 722
8.7.9 Cell Design and Layout .................................................................. 725
8.8 The Triac Structure...................................................................................... 726
8.8.1 Basic Structure and Operation........................................................ 728
8.8.2 Gate-Triggering Mode 1 ................................................................. 729
8.8.3 Gate-Triggering Mode 2 ................................................................. 730
8.8.4 [dV/dt] Capability ........................................................................... 731
8.9 Summary ..................................................................................................... 733
Problems...................................................................................................... 733
References ................................................................................................... 735
Chapter 9 Insulated Gate Bipolar Transistors ............................................ 737
9.1 Basic Device Structures .............................................................................. 741
9.2 Device Operation and Output Characteristics............................................. 745
9.3 Device Equivalent Circuit ........................................................................... 748
9.4 Blocking Characteristics ............................................................................. 748
9.4.1 Symmetric Structure Forward-Blocking Capability....................... 748
9.4.2 Symmetric Structure Reverse-Blocking Capability ....................... 753
9.4.3 Symmetric Structure Leakage Current ........................................... 754
9.4.4 Asymmetric Structure Forward-Blocking Capability .................... 760
9.4.5 Asymmetric Structure Reverse-Blocking Capability ..................... 767
9.4.6 Asymmetric Structure Leakage Current......................................... 769
9.5 On-State Characteristics.............................................................................. 776
9.5.1 On-State Model............................................................................... 776
9.5.2 On-State Carrier Distribution: Symmetric Structure...................... 783
9.5.3 On-State Voltage Drop: Symmetric Structure................................ 791
9.5.4 On-State Carrier Distribution: Asymmetric Structure.................... 796
9.5.5 On-State Voltage Drop: Asymmetric Structure ............................. 803
9.5.6 On-State Carrier Distribution: Transparent Emitter Structure ....... 808
9.5.7 On-State Voltage Drop: Transparent Emitter Structure ................. 813
9.6 Current Saturation Model............................................................................ 815
9.6.1 Carrier Distribution: Symmetric Structure ..................................... 820
9.6.2 Output Characteristics: Symmetric Structure................................. 828
9.6.3 Output Resistance: Symmetric Structure........................................ 833
9.6.4 Carrier Distribution: Asymmetric Structure................................... 834
9.6.5 Output Characteristics: Asymmetric Structure............................... 844
9.6.6 Output Resistance: Asymmetric Structure ..................................... 848
9.6.7 Carrier Distribution: Transparent Emitter Structure ...................... 849
9.6.8 Output Characteristics: Transparent Emitter Structure .................. 853
9.6.9 Output Resistance: Transparent Emitter Structure......................... 855
9.7 Switching Characteristics............................................................................ 856
9.7.1 Turn-On Physics: Forward Recovery............................................. 857
9.7.2 Turn-Off Physics: No-Load Conditions ......................................... 865
9.7.3 Turn-Off Physics: Resistive Load .................................................. 867
9.7.4 Turn-Off Physics: Inductive Load.................................................. 876
9.7.5 Energy Loss per Cycle.................................................................... 904
9.8 Power Loss Optimization............................................................................ 907
9.8.1 Symmetric Structure ....................................................................... 907
9.8.3 Transparent Emitter Structure ........................................................ 911
9.8.4 Comparison of Tradeoff Curves ..................................................... 912
9.9 Complementary (P-Channel) Structure....................................................... 913
9.9.1 On-State Characteristics ................................................................. 915
9.9.2 Switching Characteristics ............................................................... 919
9.9.3 Power Loss Optimization ............................................................... 919
9.10 Latch-Up Suppression................................................................................. 920
9.10.1 Deep P+ Diffusion........................................................................... 922
9.10.2 Shallow P+ Layer ............................................................................ 928
9.10.3 Reduced Gate Oxide Thickness...................................................... 931
9.10.4 Bipolar Current Bypass................................................................... 936
9.10.5 Diverter Structure ........................................................................... 939
9.10.6 Cell Topology ................................................................................. 943
9.10.7 Latch-Up Proof Structure ............................................................... 948
9.11 Safe Operating Area .................................................................................... 951
9.11.1 Forward-Biased Safe Operating Area ............................................ 952
9.11.2 Reverse-Biased Safe Operating Area ............................................. 956
9.11.3 Short-Circuit Safe Operating Area ................................................. 960
9.8.2 Asymmetric Structure..................................................................... 909
9.12 Trench-Gate Structure................................................................................. 966
9.12.1 Blocking Mode ............................................................................... 967
9.12.3 On-State Voltage Drop ................................................................... 971
9.12.4 Switching Characteristics ............................................................... 973
9.12.5 Safe Operating Area ....................................................................... 974
9.12.6 Modified Structures ........................................................................ 978
9.13 Blocking Voltage Scaling ........................................................................... 980
9.13.1 N-Base Design ................................................................................ 981
9.13.2 Power MOSFET Baseline .............................................................. 982
9.13.3 On-State Characteristics ................................................................. 982
9.14 High Temperature Operation ...................................................................... 986
9.14.1 On-State Characteristics ................................................................. 986
9.15
9.15.1 Electron Irradiation......................................................................... 991
9.15.2 Neutron Irradiation ......................................................................... 993
9.15.3 Helium Irradiation .......................................................................... 993
9.16 Cell Optimization ........................................................................................ 994
9.16.1 Planar-Gate Structure...................................................................... 995
9.16.2 Trench-Gate Structure .................................................................... 999
9.17 Reverse Conducting Structure................................................................... 1006
9.18 Summary ................................................................................................... 1014
Problems.................................................................................................... 1015
References ................................................................................................. 1020
Chapter 10 Synopsis........................................................................................ 1027
10.1 Typical H-Bridge Topology...................................................................... 1027
10.2 Power Loss Analysis ................................................................................. 1029
10.3 Low DC Bus Voltage Applications .......................................................... 1032
10.4 Medium DC Bus Voltage Applications .................................................... 1037
10.5 High DC Bus Voltage Applications.......................................................... 1041
10.6 Summary ................................................................................................... 1045
Problems.................................................................................................... 1045
References ................................................................................................. 1047
Author’s Biography ............................................................................................. 1049
9.14.2 Latch-Up Characteristics ................................................................ 989
Index .................................................................................................................... 1053